Integer N Frequency Synthesizer using Phase Lock Loop
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International Journal of Computer Trends and Technology (IJCTT) | 
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| © 2016 by IJCTT Journal | ||
| Volume-32 Number-1 |
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| Year of Publication : 2016 | ||
| Authors : Pallavi Patil, Virendra K. Verma | ||
| DOI : 10.14445/22312803/IJCTT-V32P102 |
Pallavi Patil, Virendra K. Verma "Integer N Frequency Synthesizer using Phase Lock Loop". International Journal of Computer Trends and Technology (IJCTT) V32(1):8-13, February 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract -
A new architecture and simulation of an
integer n frequency synthesizer using PLL for RF
application has been illustrated in this paper. This
design consists of low power phase frequency detector,
low jitter charge pump, ring oscillator based VCO,
passive loop filter and 8 bit frequency divider using
250nm technology. This presents the simplest way to
design and simulate integer n frequency synthesizer
and lock the PLL. The design and analysis of PLL is
done on simulation EDA TANNER TOOL 13.0.The
main benefit of using PLL technique in Frequency
Synthesizer is that it can generate frequencies of 100-
200MHz comparable to the accuracy of a crystal
oscillator. This paper gives a brief introduction to the
basics of Phase Locked loops.
References
[1] Neil H.E.Weste and David Money Harris ?CMOS VLSI
– A Circuits and Systems Perspective Fourth edition
[2] R.J.Baker, H.W.Li, and D.E.Boyce, ?CMOS Circuit
Design, Layout, and Simulation, IEEE Press Series on
Microelectronic Systems, 2002.
[3] Gayathri M G* “Design of All Digital Phase Locked
Loop in VHDL” Gayathri M G / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9 www.ijera.com Vol. 3, Issue 4, Jul-Aug 2013,
pp.1074-1076
[4] W. Alan Davis, Krishna Agarwal “Radio Frequency Circuit
Design” Copyright 2001 John Wiley & Sons, Inc. Print
ISBN 0-471-35052-4 Electronic ISBN 0-471-20068-9
[5] General PLL Description: T. H. Lee, Chap. 15. Gray and
Meyer, 10.4 Clock generation: B. Razavi, Design of Analog
CMOS Integrated Circuits, Chap. 15, McGraw-Hill, 2001.
[6] Vemula Lohith Kumar1 1BTech Student, School of
Electronics, Vignan University, Vadlamudi, Guntur, AP,
India ?Simulation of Integer N Frequency Synthesizer‘
International Journal of Engineering Trends and Technology
(IJCTT) - Volume4 Issue6- June 2013
[7] Kanika Garg, ACSD Department, CDAC1; V.Sulochana
Verma, ACSD Department, CDAC2 “DESIGN OF LOW
POWER PHASE LOCKED LOOP IN SUBMICRON
TECHNOLOGY” International Journal of Advanced
Technology & Engineering Research (IJATER)
[8] Yashpal Sen1 and Nitin Jain2 1M.Tech. Scholar, Dept. of
ET&T (Digital Electronics) C.E.C., Bilaspur, CSVTU,
(C.G.), INDIA. 2Dept. of E&TC, C.E.C., Bilaspur, CSVTU,
(C.G.), INDIA. ?Design and Implementation of Phase Locked
Loop Using Current Starved Voltage Controlled Oscillator
Advance in Electronic and Electric Engineering. ISSN 2231-
1297, Volume 4, Number 6 (2014), pp. 637-644 © Research
India Publications http://www.ripublication.com/aeee.htm
[9] K.Rajasekhar, S.Adilakshmi, T.B.K. Manoj kumar “Design
of High Performance Phase Locked loop for Multiple outputs
with Ultra Low Power Sub Threshold Logic” International
Journal of Engineering Research and Applications (IJERA)
ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 2,Mar-Apr
2012, pp.046-052
[10] Jyoti P. Patra and Umesh C. Pati ?Behavioural Modelling
and Simulation of PLL Based Integer N Frequency
Synthesizer using Simulink International Journal of
Electronics and Communication Engineering. ISSN 0974-
2166 Volume 5, Number 3 (2012), pp. 351-362 ©
International Research Publication House
http://www.irphouse.com
[11] Dr. P.H.Tandel, Anuradha P. Gharge ?Design of General
Order Digital Phase Locked Loop International Journal of
Engineering and Innovative Technology (IJEIT) Volume 2,
Issue 7, January 2013
[12] Abhilasha N.S “Optimized Design of Digital Phase Locked
Loops for RF Carrier Acquisition” IJESRT
(INTERNATIONAL JOURNAL OF ENGINEERING
SCIENCES & RESEARCH TECHNOLOGY) ISSN: 2277-
9655 Scientific Journal Impact Factor: 3.449 (ISRA),
Impact Factor: 1.85,1,May2014
[13] Varsha Prasad 1, Dr Chirag Sharma 2 ?A Review of Phase
Locked Loop International Journal of Emerging
Technology and Advanced Engineering Website:
www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 6, June
2012)
[14] Guan- Chyun Hsieh, senior member,IEEE, and James
C.Hung,Fellow,IEEE ?Phase- Locked Loop Techniques- A
Survey IEEE TRANSACTIONS ON INDUSTRIAL
ELECTRONICS, VOL.43,NO.6,DECEMBER 1996
[15] Anitha Babu, Bhavya Daya, Banu Nagasundaram, Nivetha
Veluchamy ?All Digital Phase Locked Loop Design and
Implementation University of Florida, Gainesville, FL,
32608, USA
[16] Curtis Barret ?Fractional/Integer-N PLL Basics Technical
Brief SWRA029
[17] B .Razvi, ?Design of ANALOG CMOS Integrated Circuits
McGraw- Hill, 2001.
[18] K. Shu, E. Sanchez-Sinencio, J. Silva-Martinez, and S.H.K.
Embabi, “A 2.4-GHz monolithic fractional-N frequency
synthesizer with robust phase-switching prescaler and loop
capacitance multiplier, IEEE Journal of Solid-State Circuits,
vol. 38, no. 6, pp. 866-874, June 2003.
[19] Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku
Moon,and Kartikeya Mayaram, ?A Design Procedure for
All-Digital Phase-Locked Loops Based on a Charge-Pump
Phase-Locked-Loop Analogy IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54,
NO. 3, MARCH 2007
[20] Kusum Lata and Manoj Kumar “ALL Digital Phase-Locked
Loop (ADPLL): A Survey” International Journal of Future
Computer and Communication, Vol. 2, No. 6, December
2013
Keywords
Phase locked loop, Phase frequency
detector, Charge pump, Loop filter, Voltage controlled
oscillator, Frequency divider.